1. Field of the Invention
The present invention relates to an amplifier circuit.
2. Description of Related Art
In the past, in a case where a differential amplifier was used as an amplifier circuit, due to slightly different properties of the transistors constituting a differential pair, there was a defect that a certain level of offset voltage was generated between output terminals of the differential amplifier, although there was no voltage difference between input terminals.
The amplifier circuit, therefore, is designed such that a negative feedback loop circuit is connected to a differential amplifier, and that by this negative feedback loop circuit, the offset voltage of the differential amplifier is amplified and fed back to the differential amplifier, so that the offset voltage of the differential amplifier is cancelled (e.g. refer to Patent Document 1).
Specifically, as illustrated in FIGS. 3 and 4, in an amplifier circuit 101, a low pass filter circuit 103 is connected to a differential amplifier 102, a buffer circuit 104 is connected to the low pass filter 103, and the buffer circuit 104 is connected to the differential amplifier 102, so that these low pass filter circuit 103 and buffer circuit 104 form a negative feedback loop circuit 105. In the figures, reference numerals 108, 109 denote input terminals of the amplifier circuit 101 and reference numerals 110, 111 denote output terminals of the amplifier circuit 101.
The low pass filter circuit 103 is constituted by a negative feedback amplifier 106 having a certain level of gain and a capacitor 107 connected in parallel between output terminals of the negative feedback amplifier 106.
In the amplifier circuit 101 having the above-described configuration, the low pass filter circuit 103 allows only a DC offset voltage to be amplified to a multiple of the gain of the negative feedback amplifier 106, without affecting a high-frequency component of an output signal of the differential amplifier 102, and to be fed back to the differential amplifier 102 via the buffer circuit 104.
[Patent Document 1]
Published Japanese Patent Application (KOKAI) No. 2003-283266